1. Related Inventions
This invention is related to: Dynamic Video Ram Incorporating on Chip Vector/Image Mode Line Modification, Ser. No. 07/277,687, filed Nov. 29, 1988 and Dynamic Video Ram Incorporating Single Clock Random Port Control, Ser. No. 07/277,637, filed Nov. 29, 1988.
2. Field of the Invention
The invention relates to a dual ported, dynamic memory designed for use in raster scan graphic applications and, more particularly, to a high density dynamic video RAM incorporating on a single integrated circuit chip drawing or replacement logical rules as well as masking operations for the modification of a line of video information stored in the memory.
3. Statement of the Problem
With the cost per bit of semiconductor memory and the price of computer systems dropping, personal work stations and other computer systems using graphics such as CAD/CAM systems are becoming more readily available. A crucial component in such systems is the dynamic video RAM which supports the graphics applications.
Conventional dynamic video RAMS, available on multichips, have a random port and a serial port enabling a computer to access the dynamic video RAM through the random port and enabling the serial port to deliver the necessary graphics information to drive, for example, a color monitor.
In designing dynamic video RAMS, several features are of critical importance.
First, it is important to package the video RAM on a single integrated circuit chip while minimizing the number of external pins from the chip. Secondly, it is important to maximize the memory contained on the chip. Third, it is important to perform as many of the modification operations on chip, rather than having off chip hardware perform these operations at a much slower rate off the chip. Fourth, it is important to maximize the addressing capabilities of the data stored within the chip.
The following patents are representative of issued patents involving dynamic RAMs commercially available. In each of these patents, no provision is made for incorporating the drawing or replacement rules onto the chip carrying the RAM. Rather, in order to modify a given line of information stored in the RAM, the information to be modified must be read out from the dynamic video RAM and modified off chip according to the acquired logical operation. The present invention performs the drawing or replacement rule with circuitry located on the chip and further is able to selectively mask the areas of modified information to be read back into the RAM.
The 1987 patent issued to Novak, et al. (U.S. Pat. No. 4,688,197) sets forth a video computer system having a RAM chip with a shift register connected to its serial output terminal which is actuated by a first clock and a second clock is utilized to load the serial chip register. The 1987 patent to Redwine et al. (U.S. Pat. No. 4,689,741) pertains to the same invention as the '197 patent but provides for coupling of data between column lines and the chip register to prevent two or more different data bits from simultaneously appearing.
The 1987 patent to Thaden (U.S. Pat. No. 4,665,495) sets forth a single chip dynamic RAM controller and CRT controller system arrangement. This invention minimizes the control circuit of prior systems thus eliminating potential bottle necks at the RAM by utilizing a single controller. A related patent also issued to Thaden et al. is U.S. Pat. No. 4,656,596.
The 1985 patent to Bruce (U.S. Pat. No. 4,546,451) sets forth a dynamic RAM which permits "page mode" addressing.
The 1987 patent to Voss (U.S. Pat. No. 4,646,270) sets forth a video graphic dynamic RAM having the capability of serially reading out data at a high rate of speed while performing standard RAM operations.
There is no disclosure in any one of the above patents of circuitry to perform drawing rule modification on chip with the random access memory.
In the target specification of the Hitachi HM53462 Multi Port DRAM, logic operation and masking occur on a single chip. However, in this approach the system must first deliver the logic operation to the chip and then cycle to address the memory, deliver the new source data, read from memory and then modify the read information.
A need exists not only for providing the drawing rule and masking circuitry on the chip with the RAM but also to maximize the performance by delivering the drawing rule with the addresses to the chip at the same time.
4. Solution to the Problem
The present invention provides a solution to the above problem by placing on an integrated circuit chip the drawing rule and masking circuitry which is responsive to the delivery of the addresses and the drawing rule at the same time so that it can execute with each address cycle.